“Verification” in an IC program is not one single gate. RTL must behave as specified, the layout must satisfy physical and connectivity rules, and the design must support manufacturing test. Three tool families within Siemens EDA for IC design answer different questions.
Questa: does the RTL behave as intended?
Questa One takes RTL, a testbench, assertions and stimulus scenarios. Simulation and suitable verification methods check behavior before physical implementation. Outputs include functional failures to fix, verification reports and coverage. High coverage indicates what has been exercised; it does not by itself prove the absence of bugs.
Calibre: does the layout match rules and connectivity?
Calibre works with the physical layout, a reference netlist and foundry rules. DRC identifies geometric rule violations. LVS compares connectivity extracted from the layout against the intended circuit. The resulting reports guide corrections before physical signoff. Passing DRC and LVS does not replace RTL functional verification.
Tessent: can manufactured silicon be tested?
Tessent supports design for test (DFT) and automatic test pattern generation (ATPG). Starting from the implemented design and test goals, engineers add appropriate test structures, generate patterns and assess test coverage. These outputs serve post-manufacturing silicon test; they do not replace DRC/LVS or RTL simulation.
How the steps connect
| Tool | Primary question | Output |
|---|---|---|
| Questa | Does RTL meet functional intent? | Failures, verification results, coverage |
| Calibre | Does layout meet rules and connectivity? | DRC/LVS reports and signoff status |
| Tessent | Can silicon be tested in production? | DFT structures, patterns and coverage |
Real programs loop between these stages: a later finding may require an earlier design change. Select the tool by the question to answer and the design data available.
Technical source: Siemens Digital Industries Software – Siemens EDA design flow white paper.
